7-19 12,000 usable pld gate pasic 3 fpga combining high performance and high density ql3012 - pasic 3 fpga tm ql3012 rev c ql3012 - pasic 3 fpga device highlights high performance & high density 12,000 usable pld gates with 118 i/os 16-bit counter speeds over 300 mhz, data path speeds over 400 mhz 0.35um four-layer metal non-volatile cmos process for smallest die sizes easy to use / fast development cycles 100% routable with 100% utilization and complete pin-out stability variable-grain logic cells provide high performance and 100% utilization comprehensive design tools include high quality verilog/vhdl synthesis advanced i/o capabilites interfaces with both 3.3 volt and 5.0 volt devices pci compliant with 3.3v and 5.0v buses for -1/-2/-3/-4 speed grades full jtag boundary scan registered i/o cells with individually controlled clocks and output enables total of 118 i/o pins 110 bidirectional input/output pins, pci-compliant for 5.0 volt and 3.3 volt buses for -1/-2/-3/-4 speed grades 4 high-drive input-only pins 4 high-drive input/distributed network pins four low-skew distributed networks two array clock/control networks available to the logic cell flip- flop clock, set and reset inputs - each driven by an input-only pin six global clock/control networks available to the logic cell f1, clock set and reset inputs and the input and i/o register clock, reset and enable inputs as well as the output enable control - each driven by an input-only or i/o pin, or any logic cell output or i/o cell feedback high performance input + logic cell + output total delays under 6 ns data path speeds over 400 mhz counter speeds over 300 mhz d evice h ighlights figure 1. 320 logic cells product summary the ql3012 is a 12,000 usable pld gate member of the pasic 3 family of fpgas. pasic 3 fpgas are fabricated on a 0.35mm four-layer metal process using quicklogic?s patented vialink technology to provide a unique combination of high performance, high density, low cost, and extreme ease-of-use. the ql3012 contains 320 logic cells. with a maximum of 118 i/os, the ql3012 is available in 84-pin plcc, 100-pin tqfp, and 144-pin tqfp packages. software support for the complete pasic 3 family, including the ql3012, is available through three basic packages. the turnkey quickworks ? package provides the most complete fpga software solution from design entry to logic synthesis, to place and route, to simulation. the quicktools tm for workstations package provides a solution for designers who use cadence, exemplar, mentor, synopsys, synplicity, viewlogic, veribest, or other third-party tools for design entry, synthesis, or simulation. p roduct s ummary
20 preliminary 7-20 ql3012 - pasic 3 fpga tm pasic pinout diagram figure 2. 84-pin plcc pasic pinout table 100-pin tqfp p asic p inout d iagram p asic p inout d iagram
7-21 ql3012 - pasic 3 fpga tm pinout diagram figure 3. 100-pin tqfp figure 4. 144-pin tqfp p inout d iagram pasic ql3012-1pf100c pin #1 pin #26 pin #76 pin #51 pasic ql3012-1pq144c pin #1 pin #173 pin #109 pin #37
22 preliminary 7-22 ql3012 - pasic 3 fpga tm 100 & 144 tqfp pinout table 100 & 144 tqfp p inout t able 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 144 tqfp 100 tqfp function 1 2 i/o 38 26 tdi 75 53 i/o 111 78 i/o 2 3 i/o 39 27 i/o 76 54 i/o 112 79 i/o 3 nc i/o 40 28 i/o 77 55 i/o 113 80 i/o 4 4 i/o 41 29 i/o 78 nc i/o 114 nc vcc 5 nc i/o 42 nc vcc 79 nc vcc 115 81 i/o 6 5 i/o 43 30 i/o 80 nc i/o 116 82 i/o 7 nc vcc 44 31 i/o 81 56 i/o 117 83 i/o 8 6 i/o 45 nc i/o 82 nc i/o 118 nc i/o 9 nc i/o 46 32 i/o 83 57 i/o 119 84 i/o 10 7 i/o 47 33 i/o 84 nc i/o 120 nc i/o 11 nc i/o 48 nc i/o 85 58 i/o 121 nc i/o 12 nc i/o 49 34 i/o 86 nc i/o 122 85 gnd 13 8 i/o 50 35 gnd 87 59 gnd 123 nc i/o 14 nc i/o 51 36 i/o 88 60 i/o 124 86 i/o 15 9 gnd 52 nc i/o 89 61 i 125 87 i/o 16 10 i/o 53 37 i/o 90 62 aclk / i 126 88 gnd 17 11 i 54 38 gnd 91 63 vcc 127 89 i/o 18 12 aclk / i 55 39 i/o 92 64 i 128 90 i/o 19 13 vcc 56 40 i/o 93 65 gclk / i 129 91 i/o 20 14 i 57 41 i/o 94 66 vcc 130 92 vccio 21 15 gclk / i 58 42 vccio 95 67 i/o 131 nc i/o 22 16 vcc 59 nc i/o 96 nc i/o 132 93 i/o 23 17 i/o 60 43 i/o nc 68 i/o 133 nc i/o 24 18 i/o 61 44 i/o 97 nc i/o 134 94 i/o 25 nc i/o 62 45 i/o 98 69 i/o 135 nc i/o 26 19 i/o 63 nc i/o 99 nc i/o 136 nc i/o 27 nc i/o 64 nc i/o 100 70 i/o nc 95 i/o 28 20 i/o 65 46 i/o 101 71 i/o 137 nc i/o 29 21 i/o 66 nc gnd 102 nc gnd 138 nc gnd 30 nc gnd 67 nc i/o 103 nc i/o 139 96 i/o 31 nc i/o 68 nc i/o 104 72 i/o 140 97 i/o 32 22 i/o 69 47 i/o 105 nc i/o 141 98 i/o 33 23 i/o 70 48 i/o 106 73 i/o 142 99 i/o 34 nc i/o 71 49 trstb 107 74 i/o 143 100 tdo 35 nc i/o 72 50 tms 108 75 i/o 144 1 i/o 36 24 i/o 73 51 i/o 109 76 tck 37 25 i/o 74 52 i/o 110 77 stm
7-23 ql3012 - pasic 3 fpga tm pin descriptions ordering information p in d escriptions pin function description tdi test data in for jtag hold high during normal operation. connect to vcc if not used for jtag. trstb active low reset for jtag hold low during normal operation. connect to ground if not used for jtag. tms test mode select for jtag hold high during normal operation. connect to vcc if not used for jtag. tck test clock for jtag hold high or low during normal operation. connect to vcc or ground if not used for jtag. tdo test data out for jtag output that must be left unconnected if not used for jtag. stm special test mode must be grounded during normal operation. i/aclk high-drive input and/or array network driver can be configured as either or both. i/gclk high-drive input and/or global network driver can be configured as either or both. i high-drive input use for input signals with high fanout. i/o input/output pin can be configured as an input and/or output. vcc power supply pin connect to 3.3v supply. vccio input voltage tolerance pin connect to 5.0 volt supply if 5 volt input tolerance is required, otherwise connect to 3.3v supply. gnd ground pin connect to ground. ql 3012 - 1 pf144 c quicklogic pasic device speed grade 0 = quick 1 = fast 2 = faster 3 = faster *4 = fastest package code pl84 = 84-pin plcc pf100 = 100-pin tqfp pf144 = 144-pin tqfp pasic 3 device part number operating range c = commercial i = industrial m = military * contact quicklogic regarding availability
24 preliminary 7-24 ql3012 - pasic 3 fpga tm absolute maximum ratings vcc voltage . . . . . . . . . . . . . . . . . . . -0.5 to 4.6v vccio voltage . . . . . . . . . . . . . . . . . -0.5 to 7.0v input voltage . . . . . . . . . . . . -0.5 to vccio +0.5v latch-up immunity . . . . . . . . . . . . . . . . . 200 ma dc input current . . . . . . . . . . . . . . . . . . . 20 ma esd pad protection . . . . . . . . . . . . . . . . . 2000v storage temperature . . . . . . . . . -65 c to +150 c lead temperature . . . . . . . . . . . . . . . . . . . 300 c operating range dc characteristics notes: [1] applies only to -1/-2/-3/-4 commercial grade devices. these speed grades are also pci-compliant. all other devices have 8 ma iol specifications. [2] capacitance is sample tested only. clock pins are 12 pf maximum. [3] only one output at a time. duration should not exceed 30 seconds. [4] for -1/-2/-3/-4 commercial grade devices only. maximum icc is 3 ma for -0 commercial grade and all industrial grade devices, and 5 ma for all military grade devices. for ac conditions, contact quicklogic customer engineering. symbol parameter military industrial commercial unit min max min max min max vcc supply voltage 3.0 3.6 3.0 3.6 3.0 3.6 v vccio i/o input tolerance voltage 3.0 5.5 3.0 5.5 3.0 5.25 v ta ambient temperature -55 -40 85 0 70 c tc case temperature 125 c -0 speed grade 0.43 1.90 0.46 1.85 k delay factor -1 speed grade 0.42 1.64 0.43 1.54 0.46 1.50 -2 speed grade 0.42 1.37 0.43 1.28 0.46 1.25 -3 speed grade n/a n/a 0.43 0.90 0.46 0.88 -4 speed grade n/a n/a 0.43 0.82 0.46 0.80 symbol parameter conditions min max unit vih input high voltage 0.5vcc vccio+0.5 v vil input low voltage -0.5 0.3vcc v voh output high voltage ioh = -12 ma 2.4 v ioh = -500 a 0.9vcc v vol output low voltage iol = 16 ma [1] 0.45 v iol = 1.5 ma 0.1vcc v ii i or i/o input leakage current vi = vccio or gnd -10 10 a ioz 3-state output leakage current vi = vccio or gnd -10 10 a ci input capacitance [2] 10 pf ios output short circuit current [3] vo = gnd -15 -180 ma vo = vcc 40 210 ma icc d.c. supply current [4] vi, vio = vccio or gnd 0.50 (typ) 2 ma iccio d.c. supply current on vccio 0 100 a
7-25 ql3012 - pasic 3 fpga tm ac characteristics at vcc = 3.3v, ta = 25 c (k = 1.00) (to calculate delays, multiply the appropriate k factor in the "operating range" section by the following numbers.) logic cells input-only/clock cells notes: [5] stated timing for worst case propagation delay over process variation at vcc=3.3v and ta=25 c. multiply by the appropriate delay factor, k, for speed grade, voltage and temperature settings as specified in the operating range. [6] these limits are derived from a representative selection of the slowest paths through the pasic 3 logic cell including typical net delays. worst case delay values for specific paths should be determined from timing analysis of your particular design. symbol parameter propagation delays (ns) fanout [5] 12348 tpd combinatorial delay [6] 1.4 1.7 1.9 2.2 3.2 tsu setup time [6] 1.7 1.7 1.7 1.7 1.7 th hold time 0.0 0.0 0.0 0.0 0.0 tclk clock to q delay 0.7 1.0 1.2 1.5 2.5 tcwhi clock high time 1.2 1.2 1.2 1.2 1.2 tcwlo clock low time 1.2 1.2 1.2 1.2 1.2 tset set delay 1.0 1.3 1.5 1.8 2.8 treset reset delay 0.8 1.1 1.3 1.6 2.6 tsw set width 1.9 1.9 1.9 1.9 1.9 trw reset width 1.8 1.8 1.8 1.8 1.8 symbol parameter propagation delays (ns) fanout [5] 123481224 tin high drive input delay 1.5 1.6 1.8 1.9 2.4 2.9 4.4 tini high drive input, inverting delay 1.6 1.7 1.9 2.0 2.5 3.0 4.5 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0 tlclk input register clock to q 0.7 0.8 1.0 1.1 1.6 2.1 3.6 tlrst input register reset delay 0.6 0.7 0.9 1.0 1.5 2.0 3.5 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 0.0
26 preliminary 7-26 ql3012 - pasic 3 fpga tm clock cells i/o cells notes: [7] the array distributed networks consist of 40 half columns and the global distributed networks consist of 44 half columns, each driven by an independent buffer. the number of half columns used does not affect clock buffer delay. the array clock has up to 8 loads per half column. the global clock has up to 11 loads per half column. [8] the following loads are used for tpxz: symbol parameter propagation delays (ns) loads per half column [7] 123481011 tack array clock delay 1.2 1.2 1.3 1.3 1.5 1.6 1.7 tgckp global clock pin delay 0.7 0.7 0.7 0.7 0.7 0.7 0.7 tgckb global clock buffer delay 0.8 0.8 0.9 0.9 1.1 1.2 1.3 symbol parameter propagation delays (ns) fanout [5] 1234810 ti/o input delay (bidirectional pad) 1.3 1.6 1.8 2.1 3.1 3.6 tisu input register set-up time 3.1 3.1 3.1 3.1 3.1 3.1 tih input register hold time 0.0 0.0 0.0 0.0 0.0 0.0 tloclk input register clock to q 0.7 1.0 1.2 1.5 2.5 3.0 tlorst input register reset delay 0.6 0.9 1.1 1.4 2.4 2.9 tlesu input register clock enable set-up time 2.3 2.3 2.3 2.3 2.3 2.3 tleh input register clock enable hold time 0.0 0.0 0.0 0.0 0.0 0.0 symbol parameter propagation delays (ns) output load capacitance (pf) 30 50 75 100 150 toutlh output delay low to high 2.1 2.5 3.1 3.6 4.7 touthl output delay high to low 2.2 2.6 3.2 3.7 4.8 tpzh output delay tri-state to high 1.2 1.7 2.2 2.8 3.9 tpzl output delay tri-state to low 1.6 2.0 2.6 3.1 4.2 tphz output delay high to tri-state [8] 2.0 tplz output delay low to tri-state [8] 1.2 5 pf 1k ? 5 pf 1k ? tphz tplz
|
